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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0V ≤ V PWR = V BAT ≤ 40V , -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OVERCURRENT COMPARATOR
Common Mode Input Range
Input Offset Voltage
Overcurrent Comparator Threshold Hysteresis (19)
V CM
V OS_OC
V OC_HYST
2.0
-50
50
–
–
V DD -0.02
50
300
V
mV
mV
Output Voltage
V
High-Level at I OH = -500μA
Low-Level at I OL = 500μA
V OH
V OL
0.85 V DD
–
–
–
V DD
0.5
HOLD OFF CIRCUIT
V DD Threshold (V DD Falling)
V DD_TH
1.5
–
4.0
V
RST pin High
Hold Off Current (At Each GATE Pin)
I HOLD
10
–
300
μA
3.0V < V BAT <
40V (20)
PHASE COMPARATOR
High-Level Input Voltage Threshold
Low-Level Input Voltage Threshold
High-Level Output Voltage at I OH = -500μA
Low-Level Output Voltage at I OL = 500μA
High-Side Source Input Resistance (19) , (23)
V IH_TH
V IL_TH
V OH
V OL
R IN
0.5 V BAT
0.3 V BAT
0.85 V DD
–
–
–
–
–
–
50
0.65 V BAT
0.45 V BAT
V DD
0.5
–
V
V
V
V
k ?
DESATURATION DETECTOR
Desaturation Detector Threshold (21)
V DES_TH
1.2
1.4
1.6
V
CURRENT SENSE AMPLIFIER
Recommended External Series Resistor (See Figure 9 )
Recommended External Feedback Resistor (See Figure 9 )
R S
R FB
–
5.0
1.0
–
–
15
k ?
k ?
Limited by the Output Voltage Dynamic Range
Maximum Input Differential Voltage (See Figure 9 )
V ID
-800
–
+800
mV
V ID = V AMP_P - V AMP_N
Input Common Mode Range (19) , (22)
Input Offset Voltage
V C Μ
V OS
0
-15
–
–
3.0
+15
V
mV
R S = 1k ? , V CM = 0.0V
Input Offset Voltage Drift (19)
Input Bias Current
δ V OS / δ T
I b
–
-200
-10
–
–
+200
μV/°C
nA
V CM = 2.0V
Notes
19. This parameter is a design characteristic, not production tested.
20. The hold off circuit is designed to operate over the full operating range of V BAT . The specification indicates the conditions used in
production test.
21. Desaturation is measured as the voltage drop below V BAT , thus the threshold is compared to the drain-source voltage of the external
high-side FET. See Figure 5 .
22. As long as one input is within V CM the output is guaranteed to have the correct phase. Exceeding the common mode rails will not cause
a phase inversion on the output.
23. Input resistance is impedance from high-side source and is referenced to ground. Approximate tolerance is ±20%.
33927
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
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